Can a cost model trained on other chip-design families screen a new family’s Pareto front with a handful of syntheses?
research/eda-screenxfer
A Pareto screen whose cell-count model was trained only on other design families reaches 0.94 to 0.98 of the true front's hypervolume with 3 Yosys syntheses (random about 0.65), though the model's absolute error is large; ranking is what matters (stylised, MAC and FIR spaces of 27 designs).
What it found
A follow-up to eda-screen and eda-adapt on 100 sampled 27-design spaces of two families (MAC engine, FIR filter). A screen whose cell-count model was trained only on the other families reaches 0.94 to 0.98 of the true front’s hypervolume with 3 Yosys syntheses and about 1.00 by 8, against 0.83 to 0.85 for random search at 8. The cost model’s absolute error is large (median 22–222% for ridge), but its ranking is what the screen uses; refitting on the screen’s own syntheses adds little, and spending the first syntheses on an adaptation spread hurts at tiny budgets. Stylised: tiny fronts (3–5 designs), generic-cell counts, one free objective, no place and route.
A figure from its own output
Paper, code and results
More in Algorithmic chip-design loops
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- How many injected RTL bugs do random, coverage-directed and formal checks catch, and at what cost?Mutation study of random, coverage-directed and bounded-formal RTL checks on the MAC accelerator: 64 random vectors kill 99% of killable mutants, formal 71% (timeouts), at ~50x the CPU cost (stylised).
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- When can a check cascade stop formal verification early without losing kills?Replays the eda-verify log with a time cap on formal: a 170 s cap loses no kill and saves 41% of cascade CPU but forfeits every equivalence proof; a 230 s cap keeps 15 of 16 proofs and saves 23% (stylised re-analysis).
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Proper scoring & elicitation28Effort & peer prediction9Verification games & slashing19Detection & tolerances14Markets as routers13Prediction-market design9Paying contributors8Decentralised training systems23Digital twins & sim-to-real164LLM chip design loops40Robot manufacturing loops53Ambient AI assistant46Self-replicating manufacturing34Simulation-first design64Engineered clothing45Task-specific AI accelerators40Algorithmic chip-design loops42Open-source purpose-built robots44The software-engineering loop43Adversarial human imitation41Open-source residential construction41Autonomous multi-angle capture34Sensing, imaging and 3D31Energy supply and dense energy storage39Robot societies among people31Agentic co-design of low-cost robots27Laundry-hanging robots25Machine learning on qualitative data23Robots on the building site27Civilizations & group psychology1History & human sciences1
Produced with AI assistance (Claude). Results are from the code in this repository and are simulated or stylised unless the abstract says otherwise; nothing here implies affiliation with or endorsement by any lab, researcher or company cited. MIT licensed.