Does the farthest-point spread's lead over random draws, when adapting a chip-design cost model to a new family, survive resampling the designs themselves?
research/eda-adaptdesign
eda-adaptci re-run with a design-level bootstrap: the intervals widen by up to 2.5x, the spread's lead holds at 5 and 8 designs for both models (about 0.5 to 1.1 points) and at 2 for the linear model, but the linear k = 3 lead and the ridge k = 2 lead include zero, and the ridge k = 3 loss reported earlier is not established.
What it found
Same 133 Yosys-synthesised designs in four families as eda-adaptci, whose intervals resampled (family, split) cells that reuse the same designs. Here each bootstrap replicate redraws every family's designs with replacement and recomputes the median paired gap APE(spread) − APE(random) over 160 cells. The spread beats random draws at k = 5 and 8 for linear and ridge (design-level intervals −1.18 to −0.15 and −1.82 to −0.34 at k = 5) and at k = 2 for linear, but the linear k = 3 and ridge k = 2 intervals now include zero, and the ridge k = 3 loss is +1.16 with interval −0.64 to +3.31. Intervals are up to about 2.5 times as wide as the cell bootstrap. Limitations: four hand-written families, ~33 designs each, pool designs not resampled, untuned weights, Yosys cell counts rather than post-route PPA; no input is assumed beyond the committed dataset.
A figure from its own output
Paper, code and results
More in Algorithmic chip-design loops
- How many placed designs from a new family does an area surrogate need, and does the answer change when the target is placed area instead of a synthesis cell count?The eda-adapt few-shot curves refitted to OpenROAD-placed area on 133 SKY130 designs: an unseen family's placed area is off by 39% (ridge), one placed design cuts it to 23%, about three reach 20%, as for cell counts.
- Do input-biased random vectors (extreme, sparse, one-hot) catch RTL bugs that uniform random vectors never did?Four biased generators (20,000 vectors per target) catch none of the 26 eda-deepdraw survivors, so none contradicts a formal equivalence proof, and the del@122 mutant is confirmed as truncated output (90 rows for 100 vectors).
- Do the SKY130 area and latency conclusions for a MAC-engine family survive a target clock period?The 40 MAC-engine designs mapped to SKY130 at six shared clock targets: cell count still ranks area (Spearman 0.995+), logic depth ranks delay at only 0.34 to 0.82, and with one shared clock the Pareto front equals the generic one, so the earlier front change came from per-design clocks.
- Do 20,000 random vectors catch any RTL bug that 64 missed, and do they contradict the formal equivalence proofs?20,000 further random vectors catch none of the 25 eda-verify survivors, so none contradicts a formal equivalence proof; a random-visible bug among the 9 formal timeouts has per-vector detection probability below 1.4e-4.
- Can a library-free delay estimate rank accelerator designs by SKY130 critical-path delay better than logic depth?Library-free delay proxies on the generic gate netlist of the 40 MAC engines: gate-type weights leave depth's Spearman 0.611 against SKY130-mapped delay unchanged (0.609), adding fan-out lifts it to 0.83 to 0.90, but gate count alone reaches 0.911, and no proxy recovers the true (area, latency) front.
- How many random vectors does it take to see an RTL bug, and what can 1,280 clean vectors not rule out?Per-vector detection probabilities of the eda-verify mutants: a geometric model fits the random-vector miss rate within 0.005, predicts 45 vectors for a 1% miss, and 1,280 clean vectors cannot rule out a bug rarer than 0.0023 per vector (stylised re-analysis).
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Produced with AI assistance (Claude). Results are from the code in this repository and are simulated or stylised unless the abstract says otherwise; nothing here implies affiliation with or endorsement by any lab, researcher or company cited. MIT licensed.