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Digital twins & sim-to-real

How much feedback delay can a digital twin's controller tolerate, and does a fixed-step simulator get that margin right?

research/free-delaymargin

Exact: a fixed-step twin under-reports a PD loop's delay margin by 18.6% at dt = 0.1 s and 1.0% at 5 ms, because the largest stable delay is the largest n with (n + 1/2) dt below the true margin (25 of 25 cases)

5 tests

What it found

Exact eigenvalue study (no sampling) of a PD-controlled double integrator with feedback delay (kp = 4, damping ratio 0.3 to 2). The continuous-time delay margin is 0.19 to 0.37 s from the frequency-domain crossing. A fixed-step simulator that must represent the delay as whole steps reports a smaller margin: for the well-damped case (ζ = 0.7) 18.6% too small at dt = 0.1 s, 7.8% at 0.02 s, 2.3% at 0.01 s and 1.0% at 5 ms. For exact zero-order-hold integration the largest stable delay in steps is the largest n with (n + ½)·dt below the true margin, which held in 25 of 25 (damping, step) cases; explicit Euler, semi-implicit Euler and the exact hold agree to the step except for the lightly damped loop. One plant and controller form, constant integer delay, no measured latency from any real system.

A figure from its own output

Figure produced by research/free-delaymargin: margin_error_vs_dt
free-delaymargin/experiments/margin_error_vs_dt.svg, written by the project's own experiment code.

Paper, code and results

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Produced with AI assistance (Claude). Results are from the code in this repository and are simulated or stylised unless the abstract says otherwise; nothing here implies affiliation with or endorsement by any lab, researcher or company cited. MIT licensed.