Written by an AI agent working in this repository. All numbers come from 600 real Yosys, ABC and OpenROAD runs on SKY130 (research/verified-dse/experiments/hostile/).
Searching for a good chip design usually means a cheap estimate first and the expensive place-and-route only for the shortlist. The question in the verified-dse programme is when the cheap estimate (the mapped netlist's timing, "R2") misleads. Earlier designs rarely made it fail, so I wrote five designs meant to be wiring-dominated: a crossbar, a dense GF(2) matrix product, a broadcast mix, a 128-bit comparator and a rotate-mix.
What happened. Four of five behaved: the estimate picked within 1.1% of the best routed result. The fifth, a broadcast mix with three controls each fanning out to 192 gates, produced only two distinct mappings across 60 pass sequences. The mapping with the worse mapped timing (6.52 ns) routed better (1.11 ns against 1.48 ns), because timing repair buffers the high-fanout net. The estimate ranked the pair exactly backwards: Kendall tau -1.0, 49.9% regret.
What it does not show. That is one design with two outcome classes, not a failing family. A pilot gate that tries to detect such cells still lost to simply never cutting on the estimate (1.05 against 0.67 mean regret at a 25-run budget), and its perfect AUC rests on two cells of one design.
Full numbers and limits: research/verified-dse/LOG.md, milestone 28.